The invention generally relates to an amplifier that indicates its degree of calibration, such as an amplifier that is used in a stage of a pipelined analog-to-digital converter, for example.
An analog-to-digital converter (ADC) typically is used to form an interface between a computer and its surroundings. As an example, a sensor, such as a microphone, may generate an analog signal that indicates sounds that are sensed by the microphone, and the computer may process or store indications of the sounds. However, because the computer typically processes digital data, an ADC may be used to convert the analog signal into a digital signal, a representation that is recognized by the computer.
An ADC is effectively a collection of analog devices that are fabricated on the same semiconductor die along with digital devices. Unfortunately, the fabrication process may be tailored to optimize performance of the digital devices. As a result, the fabrication process may not permit precise fabrication of sensitive analog devices of the ADC, a constraint that may compromise the accuracy of the ADC.
For example, referring to FIG. 1, one type of ADC is a pipelined ADC 10, a circuit that converts an analog input signal (called V.sub.IN) into a digital signal by using a successive approximation technique to produce bits of the digital signal. More particularly, the ADC 10 may be formed from N pipelined stages 12 (stages 12.sub.1, 12.sub.2 and 12.sub.N, as examples), each of which indicates one bit of an N bit digital signal. The ADC 10 produces the bits of the digital signal one stage 12 at a time, beginning with the most significant bit (that appears at the output terminal of the stage 12.sub.1) and continuing in an ordered sequence along the pipeline to eventually produce the least significant bit (that appears at the output terminal of the stage 12.sub.N) when the conversion is complete. To begin the conversion, the stage 12.sub.1, (that is associated with the most significant bit) receives the V.sub.IN analog input signal, and a comparator 14 (of the stage 12.sub.1) compares the V.sub.IN analog input signal to a reference analog signal (called V.sub.REF), a comparison that produces an indication of the most significant bit at the comparator's output terminal, a terminal that forms the output terminal of the stage 12.sub.1. The V.sub.IN analog input signal passes through an amplifier 16 that multiplies the V.sub.IN analog input signal by two, a bit order adjustment in preparation for the comparison by the lower bit order stage 12.sub.2. The output signal of the amplifier 16, in turn, is received by an adder 18 (of the stage 12.sub.1) that adds either the V.sub.REF analog reference signal or a -V.sub.REF analog reference signal to the output signal of the amplifier 16 to produce a signal (at the output terminal of the adder 18) depending on the output of comparator 14.
In this manner, when the comparator determines that V.sub.IN is greater than V.sub.REF, V.sub.REF is subtracted from the amplifier 16 output. Similarly, when V.sub.IN is less than V.sub.REF, V.sub.REF is added to the amplifier 16 output. This output of the adder 18 signal is known as the residue and is received by an input terminal of a comparator 14 of the stage 12.sub.2 that, along with the other stages 12, function similarly to the stage 12.sub.1, to produce the other bits of the digital signal.
The gain (ideally two) of the amplifier 16 contributes significantly to the overall accuracy of the ADC 10. The offset error may be corrected by other architectural changes not disclosed here so the gain become the dominant error contributor. The amplifier 16 may be, for example, a switched capacitor amplifier that uses a ratio of capacitances to establish its gain. Unfortunately, the digital process that may be used to fabricate the capacitors of the amplifier 16 may not permit the formation of capacitors that have precise capacitances. As a result, the actual gain of the amplifier 16 may be substantially different from the ideal gain of two, and thus, the inaccuracy that is introduced by the amplifier 16 may limit the overall accuracy of the ADC 10.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.